SH7727 Datasheet, PDF (471/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Start
Initial settings
(SAR, DAR, DMATCR, CHCR, DMAOR)
DE, DME = 1 and
No
AE, NMIF, TE = 0?
Yes
Transfer request
No
occurs?^*1
Yes
Transfer (1 transfer unit);
DMATCRD1 → DMATCR, SAR and DAR
updated
*2
Bus mode,
*3
transfer request mode,
DREQ detection selection
system
No
DMATCR = 0?
Yes
DEI interrupt request (when IE = 1)
Does
AE = 1 or NMIF = 1 or ^No
DE = 0 or DME
= 0?
Yes
Transfer end
Does
AE = 1 or NMIF = 1 or
No
DE = 0 or DME
= 0?
Yes
Transfer aborted
Normal end
Notes: 1. In auto-request mode, transfer begins when AE, NMIF and TE are all 0 and the DE and
DME bits are set to 1.
2. DREQ = level detection in burst mode (external request) or cycle-steal mode.
3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst
mode.
Figure 14.2 DMAC Transfer Flowchart
Rev. 5.00 Dec 12, 2005 page 399 of 1034
REJ09B0254-0500