SH7727 Datasheet, PDF (521/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 15 Timer (TMU)
Bit: 31
30
29
28
27
26
25
24
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
20
19
18
17
16
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
9
8
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
15.2.4 Timer Counters (TCNT)
The TMU has a total of three timer counters (TCNT), one for each channel. The TCNT counters
are 32-bit read/write registers that are decremented according to the input clock. The input clock
can be selected with the TPSC2 to TPSC0 bits in the timer control register (TCR).
When a TCNT decrementation results in an underflow (H'00000000 → H'FFFFFFFF), the
underflow flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR
value is simultaneously set in TCNT itself and the decrementation continues from that value.
The TCNT counter is a 32-bit readable/writable register. Because the internal bus for the SH7727
on-chip peripheral modules is 16 bits wide, a time lag occurs when reading data from 32-bit
registers because the upper 16 bits and lower 16 bits are read separately. Since TCNT counts
sequentially, this time lag can create discrepancies between the data in the upper and lower halves.
To prevent this, a buffer register is connected to TCNT so that upper and lower halves are not read
separately. Thus all 32 bits in TCNT can thus be read at once and no timing discrepancies occur
when reading data.
Rev. 5.00 Dec 12, 2005 page 449 of 1034
REJ09B0254-0500