SH7727 Datasheet, PDF (708/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
(2) Control Data
Control data is read out/written into the following registers.
• Writing transmit control data: SITCR register (32 bit access)
• Reading receive control data: SIRCR register (32 bit access)
Figure 20.6 shows bit alignments of transmit or receive data and SITCR and SIRCR registers.
(a) At the control data 1ch.
31
24 23
16 15
87
0
Control data ch. 0
(b) At the control data 2ch.
31
24 23
16 15
87
0
Control data ch. 0
Control data ch. 1
Figure 20.6 Control Data Bit Alignment
The channel number of control data is set with CD0E bit CD1E bit of SICDAR register.
Table 20.8 establishment of ch. number for control data. Use channel 0 when using only data one
channel as control data.
Table 20.8 Control Data Channel Number Establishment
Ch. Number
1
2
CD0E
1
1
Bit
CD1E
0
1
Rev. 5.00 Dec 12, 2005 page 636 of 1034
REJ09B0254-0500