SH7727 Datasheet, PDF (898/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 26 Pin Function Controller (PFC)
26.2 Register Configuration
Table 26.2 summarizes the registers of the pin function controller (PFC).
Table 26.2 Pin Function Controller Registers
Name
Port A control register
Port B control register
Port C control register
Port D control register
Port E control register
Port F control register
Port G control register
Port H control register
Port J control register
Port K control register
Port L control register
SC port control register
Abbreviation R/W
PACR
R/W
PBCR
R/W
PCCR
R/W
PDCR
R/W
PECR
R/W
PFCR
R/W
PGCR
R/W
PHCR
R/W
PJCR
R/W
PKCR
R/W
PLCR
R/W
SCPCR
R/W
Initial Value Address
Access Size
H'0000
H'04000100 16
(H'A4000100)*
H'0000
H'04000102 16
(H'A4000102)*
H'AAAA
H'04000104 16
(H'A4000104)*
H'AAAA
H'04000106 16
(H'A4000106)*
H'AAAA/H'2AA8 H'04000108 16
(H'A4000108)*
H'AAAA/H'00AA H'0400010A 16
(H'A400010A)*
H'AAAA/H'A200 H'0400010C 16
(H'A400010C)*
H'AAAA/H'8AAA H'0400010E 16
(H'A400010E)*
H'0000
H'04000110 16
(H'A4000110)*
H'0000
H'04000112 16
(H'A4000112)*
H'0000
H'04000114 16
(H'A4000114)*
H'8008
H'04000116 16
(H'A4000116)*
Port M control register PMCR
R/W H'AAAA
H'04000118 16
(H'A4000118)*
Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on,
either access these registers from the P2 area of logical space or else make an appropriate
setting using the MMU so that these registers are not cached.
If a low level is input at the ASEMD0 pin while the RESETP pin is asserted, ASE mode is
entered; if a high level is input, normal mode is entered. See section 31, User-Debugging
Interface (H-UDI), for more information on the H-UDI.
The initial value of the port E, F, G, and H control registers depends on the state of the
ASEMD0 pin.
* When address translation by the MMU does not apply, the address in parentheses
should be used.
Rev. 5.00 Dec 12, 2005 page 826 of 1034
REJ09B0254-0500