SH7727 Datasheet, PDF (523/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

15.3 TMU Operation
Section 15 Timer (TMU)
15.3.1 Overview
Each channel has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR). The
TCNT is a down-counter. The auto-reload function can be used to enable synchronized counting
and counting by external events.
15.3.2 Basic Functions
Counter Operation: When the STR0 to STR2 bits in the timer start register (TSTR) are set, the
corresponding timer counters (TCNT) start decrementation. When TCNT underflows, the UNF
flag in the corresponding timer control register (TCR) is set. At this time, if the UNIE bit in TCR
is 1, an interrupt request is sent to the CPU. Also at this time, the value is copied from TCOR to
TCNT and the decrementation is continued.
The decrementation is set as follows (figure 15.2):
Select operation
Select counter
clock
(1)
Set underflow
interrupt generation
(2)
Set timer constant
register
(3)
Initialize timer
counter
(4)
(1) Select the counter clock with the TPSC2
to TPSC0 bits in the timer control register
(TCR).
(2) Set whether or not an interrupt is
generated when TCNT underflows, with
the UNIE bit in TCR.
(3) Set a value in the timer constant register
(TCOR) (the cycle is the set value plus 1).
(4) Set the initial value in the timer counter
(TCNT).
(5) Set the STR bit in the timer start register
(TSTR) to 1 to start operation.
Start counting
(5)
Note: When an interrupt has been generated, clear the flag in the interrupt handler that
caused it.
If interrupts are enabled without clearing the flag, another interrupt will be generated.
Figure 15.2 Setting the Count Operation
Rev. 5.00 Dec 12, 2005 page 451 of 1034
REJ09B0254-0500