SH7727 Datasheet, PDF (1017/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Stable input clock
EXTAL input,
CKIO input
PLL synchronization
PLL output,
CKIO output
Internal clock
Section 32 Electrical Characteristics
IRQ4−IRQ0/IRL3−IRL0
interrupt request
Stable input clock
t_IRLSTB
t_PLL1
PLL synchronization
STATUS0
STATUS1
Normal
Standby
Normal
Note: PLL oscillation setting time when clock is input from EXTAL pin or CKIO pin in continuous
oscillation mode.
Figure 32.11 PLL Synchronization Settling Time by IRQ/IRL and PINT0/1 Interrupt
Multiplier factor change
EXTAL input^*1
CKIO output^*2,
PLL output
Internal clock
t_PLL2
Notes: 1. Clock mode 7, CKIO input.
2. Clock mode 7, PLL output.
Figure 32.12 PLL Sync Stabilization Time at Frequency Multiplier Factor Change
Rev. 5.00 Dec 12, 2005 page 945 of 1034
REJ09B0254-0500