SH7727 Datasheet, PDF (824/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 24 USB HOST Module
Register: HcRhPortStatus[1:2]
Bits
Reset
R/W
31–21 0h
—
20
0
R/W
19
0
R/W
18
0
R/W
17
0
R/W
Offset: 54–57, 58–5B
Description
Reserved.
PortResetStatusChange (PRSC)
This bit is set when the 10 ms port reset signal has completed.
Writing a 1 clears this bit writing a 0 has no effect.
0 = Port reset is not complete.
1 = Port reset is complete.
PortOverCurrentIndicatorChange (OCIC)
This bit is valid when an over-current condition is reported on
the base of each port. This bit is set when the root hub changes
the PortOverCurrentIndicator bit. Writing a 1 clears this bit.
Writing a 0 has no effect.
0: PortOverCurrentIndicator has not changed. (initial value)
1: PortoverCurrentIndicator has changed.
PortSuspendStatusChange (PSSC)
This bit is set when all resume sequences have completed.
These sequences include 20 ms resume pulse, LS EOP, and 3
ms resychronization delay. Writing a 1 clears this bit. Writing a
0 has no effect. This bit is cleared also when
ResetStatusChange is set.
0: Port resume has not completed. (initial value)
1: Port resume has completed.
PortEnableStatusChange (PESC)
This bit is set when the PortEnableStatus bit is cleared due to a
hardware event . This bit is not set by the change of writing of
HCD. Writing a 1 clears this bit. Writing a 0 has no effect.
0: PortEnableStatus has not changed (initial value)
1: PortEnableStatus has changed
Rev. 5.00 Dec 12, 2005 page 752 of 1034
REJ09B0254-0500