SH7727 Datasheet, PDF (871/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

25.3.4 Data Format
1. Packed 1bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format]
MSB
LSB
Address
7 6 5 4 3 2 1 0 [Bit]
+00
P00 P01 P02 P03 P04 P05 P06 P07 (Byte0)
+01
P08
(Byte1)
+02
+03
…
…
+LAO+00
+LAO+01
+LAO+02
+LAO+03
…
P10 P11 P12 P13 P14 P15 P16 P17
P18
…
Display Memory
2. Packed 2bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format]
Address
+00
MSB
76
P00
54
P01
32
P02
LSB
1 0 [Bit]
P03 (Byte0)
+01
P04 P05 P06 P07 (Byte1)
+02
+03
…
…
+LAO+00 P10
P11
P12
P13
+LAO+01 P14
P15
P16
P17
+LAO+02
…
+LAO+03
…
Display Memory
3. Packed 4bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format]
MSB
LSB
Address
7 6 5 4 3 2 1 0 [Bit]
+00
P00
P01
(Byte0)
+01
P02
P03
(Byte1)
+02
P04
P05
(Byte2)
+03
…
…
+LAO+00
+LAO+01
+LAO+02
+LAO+03
…
P00
P01
P02
P03
P04
P05
…
Display Memory
4. Packed 1bpp (Pixel Alignment in Byte is Little Endian)
MSB
LSB
Address
7 6 5 4 3 2 1 0 [Bit]
+00
P07 P06 P05 P04 P03 P02 P01 P00 (Byte0)
+01
P08 (Byte1)
+02
+03
…
…
+LAO+00
+LAO+01
+LAO+02
P17 P16 P15 P14 P13 P12 P11 P10
P18
…
+LAO+03
…
Display Memory
Section 25 LCD Controller
↓ Top Left Pixel
P00 P01 P02 P03 P04 P05 P06 P07 ^…
P10 P11 P12 P13 P14 P15 P16 P17 ^…
…
…
Display
Pn: Put 1bit data
LAO: Line Address Offset
Unused bits should be 0
↓ Top Left Pixel
P00 P01 P02 P03 P04 P05 P06 P07 ^…
P10 P11 P12 P13 P14 P15 P16 P17 ^…
…
…
Display
Pn=Pn[1:0]: Put 2bit data
LAO: Line Address Offset
Unused bits should be 0
↓ Top Left Pixel
P00 P01 P02 P03 P04 P05 P06 P07 ^…
P10 P11 P12 P13 P14 P15 P16 P17 ^…
…
…
Display
Pn=Pn[3:0]: Put 4bit data
LAO: Line Address Offset
Unused bits should be 0
↓ Top Left Pixel
P00 P01 P02 P03 P04 P05 P06 P07 ^…
P10 P11 P12 P13 P14 P15 P16 P17 ^…
…
…
Display
Pn: Put 1bit data
LAO: Line Address Offset
Unused bits should be 0
Rev. 5.00 Dec 12, 2005 page 799 of 1034
REJ09B0254-0500