SH7727 Datasheet, PDF (570/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 17 Serial Communication Interface (SCI)
Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted, the SCTDR did not contain valid data, so transmission has ended. TEND is a read-
only bit and cannot be written.
Bit 2: TEND
0
1
Description
Transmission is in progress
[Clear condition]
When TDRE=1 is read and then 0 is written to TDRE.
End of transmission
(Initial value)
[Setting conditions]
1. When the chip is reset or enters standby mode
2. When TE is cleared to 0 in the serial control register (SCSCR)
3. If TDRE is 1 when the last bit of a one-byte serial character is transmitted.
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data
when a multiprocessor format is selected for receiving in the asynchronous mode. The MPB is a
read-only bit and cannot be written.
Bit 1: MPB
Description
0
Multiprocessor bit value in receive data is 0*
(Initial value)
1
Multiprocessor bit value in receive data is 1
Note: * If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its
previous value.
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format is selected for transmitting in the asynchronous mode.
The MPBT setting is ignored in the clock synchronous mode, when a multiprocessor format is not
selected, or when the SCI is not transmitting.
Bit 0: MPBT
0
1
Description
Multiprocessor bit value in transmit data is 0
Multiprocessor bit value in transmit data is 1
(Initial value)
Rev. 5.00 Dec 12, 2005 page 498 of 1034
REJ09B0254-0500