SH7727 Datasheet, PDF (769/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 23 USB Function Controller
23.5.8 USB Interrupt Flag Register 1 (USBIFR1)
Together with USB interrupt flag register 0, USBIFR1 indicates interrupt status information
required by the application. When an interrupt source occurs, the corresponding bit is set to 1 and
an interrupt request is sent to the CPU according to the combination with USB interrupt enable
register 1. Clearing is performed by writing 0 to the bit to be cleared, and 1 to the other bits.
Bit:
7
6
5
4
3
2
1
0
—
—
—
— VBUSMN EP3
EP3 VBUSF
TR
TS
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R/W
R/W
R/W
Bits 7 to 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—USB Connect Status (VBUSMN): This bit is a status bit for monitoring the state of the
USBF_VBUS pin. It reflects the state of the USBF_VBUS pin.
Bit 2—EP3 Transfer Request (EP3 TR): This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 3 is received from the host. A NACK handshake is
returned to the host until data is written to the FIFO buffer and packet transmission is enabled.
Bit 1—EP3 Transmit Complete (EP3 TS): This bit is set when data is transmitted to the host
from endpoint 3 and an ACK handshake is returned.
Bit 0—USB Bus Connect (VBUSF): This bit is set to 1 when connecting to or disconnecting
from the USB bus. The USBF_VBUS pin is used to detect connection/disconnection.
The USBF_VBUS pin must be connected, as it is needed inside the module.
Rev. 5.00 Dec 12, 2005 page 697 of 1034
REJ09B0254-0500