SH7727 Datasheet, PDF (607/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 17 Serial Communication Interface (SCI)
Error processing
No
ORER = 1?
Yes
Overrun error processing
Clear ORER bit in SCSSR to 0
End
Figure 17.21 Sample Serial Reception Flowchart (2)
In receiving, the SCI operates as follows:
1. The SCI synchronizes with serial clock input or output and initializes internally.
2. Receive data is shifted into the SCRSR in order from the LSB to the MSB. After receiving the
data, the SCI checks that RDRF is 0 so that receive data can be loaded from the SCRSR into
the SCRDR. If this check is passed, the SCI sets RDRF to 1 and stores the received data in the
SCRDR. If the check is not passed (receive error), the SCI operates as indicated in table 17.12.
This state prevents further transmission or reception. While receiving, the RDRF bit is not set
to 1. Be sure to clear the error flag.
3. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the
SCSCR, the SCI requests a receive-data-full interrupt (RXI). If the ORER bit is set to 1 and the
receive-data-full interrupt enable bit (RIE) in the SCSCR is also set to 1, the SCI requests a
receive-error interrupt (ERI).
Figure 17.22 shows an example of the SCI receive operation.
Rev. 5.00 Dec 12, 2005 page 535 of 1034
REJ09B0254-0500