SH7727 Datasheet, PDF (481/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
(2) In the indirect address transfer mode
The address of the memory in which data to be transferred is stored is specified in the transfer
source address register (SAR3) in the DMAC. 16-byte transfer is not provided in this mode.
The address value specified in the transfer source address register in the DMAC is read first,
and this value is temporarily stored in the DMAC. Next, the read value is output as an address,
and data on that address is stored in in the DMAC again. Then, the value read afterwards is
written to the address specified by the transfer destination address register; thus one DMA
transfer is completed.
Figure 14.9 shows an example of this operation. In this example, the transfer destination,
transfer source, and storage destination of the indirect address are all in external memories, and
the transfer data size is 16 or 8 bits. Figure 14.10 shows an example of the transfer timing.
In this mode, one NOP cycle (CK1 cycle shown in figure 14.10) is required to output data
which was read as an indirect address to an address bus.
For a 32-bit data transfer, third and fourth bus cycles shown in figure 14.10 are required twice
for each; a total of six bus cycles and one NOP cycle are required.
Rev. 5.00 Dec 12, 2005 page 409 of 1034
REJ09B0254-0500