SH7727 Datasheet, PDF (238/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 7 Interrupt Controller (INTC)
7.1.2 Block Diagram
Figure 7.1 is a block diagram of the INTC.
NMI
IRL3 to IRL0
IRQ0 to IRQ5
PINT0 to PINT15
4
Input
6
control
16
DMAC
SIOF
SCIF
SCI
ADC
TMU
RTC
WDT
REF
H-UDI
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(refresh request)
(Interrupt request)
Priority
identifier
Com-
parator
Interrupt
request
SR
3210
CPU
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
PCC
LCDC
USBH
USBF
AFE
ICR
IPR
IPRA to IPRG
Legend:
TMU:
RTC:
SCI:
SCIF:
WDT:
REF:
ICR:
IPRA to IPRG:
SR:
Timer unit
Realtime clock unit
Serial communication interface
Serial communication interface (with FIFO)
Watchdog timer
Refresh requests in the bus state controller
Interrupt control register
Registers A-E for setting the interrupt
proprity levels
Status register
Bus
interface
INTC
DMAC:
ADC:
H-UDI:
PCC:
LCDC:
USBH:
USBF:
AFE:
SIOF:
Direct memory access controller
Analog-to-digital converter
Hitachi user-debugging interface
PCMCIA controller
LCD controller
USB host
USB function controller
AFE interface
Serial IO
Figure 7.1 INTC Block Diagram
Rev. 5.00 Dec 12, 2005 page 166 of 1034
REJ09B0254-0500