SH7727 Datasheet, PDF (568/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 17 Serial Communication Interface (SCI)
Bit 6—Receive Data Register Full (RDRF): Indicates that SCRDR contains received data.
Bit 6: RDRF Description
0
SCRDR does not contain valid received data
(Initial value)
[Clear conditions]
1. When the chip is reset or enters standby mode
2. When software reads RDRF after it has been set to 1, then writes 0 in RDRF.
1
SCRDR contains valid received data
[Setting condition]
When serial data is received normally and transferred from SCRSR to SCRDR.
Note:
The SCRDR and RDRF are not affected by detection of receive errors or by clearing of the
RE bit to 0 in the serial control register. They retain their previous contents.
If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER)
occurs and the received data is lost.
Bit 5—Overrun Error (ORER): Indicates that data reception aborted due to an overrun error.
Bit 5: ORER Description
0
Receiving is in progress or has ended normally^*1
(Initial value)
[Clear conditions]
1. When the chip is reset or enters standby mode
2. When ORER=1 is read and then 0 is written to ORER.
1
A receive overrun error occurred^*2
[Setting condition]
When reception of the next serial data ends when RDRF is set to 1.
Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which
retains its previous value.
2. SCRDR continues to hold the data received before the overrun error, so subsequent
receive data is lost. Serial receiving cannot continue while ORER is set to 1. In the
clock synchronous mode, serial transmitting is also disabled.
Rev. 5.00 Dec 12, 2005 page 496 of 1034
REJ09B0254-0500