SH7727 Datasheet, PDF (75/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 1 Overview and Pin Functions
Item
DSP
Features
• Mixture of 16-bit and 32-bit instructions
• 32-/40-bit internal data bus
• Multiplier, ALU, barrel shifter and DSP register
• 16 bits x 16 bits → 32-bit one cycle multiplier
• Large DSP data register
 Six 32-bit data registers
 Two 40-bit data registers
• Extended Harvard Architecture for DSP data bus
 Two data buses
 One instruction bus
• Max. four parallel operations: ALU, multiply and two load or store
• Two addressing units to generate addresses for two memory access
• DSP data addressing modes: increment, indexing (with or without modulo
addressing)
• Zero overhead repeat loop control
• Conditional execution instructions
• User-DSP mode and privileged-DSP mode
Clock pulse
• Clock mode: An input clock can be selected from the external input (EXTAL
generator (CPG)
or CKIO) or crystal oscillator.
• Three types of clocks generated:
 CPU clock: 1–16 times the input clock
 Bus clock: 1–4 times the input clock
 Peripheral clock: 1/4–4 times the input clock
• Power-down modes:
 Sleep mode
 Standby mode
 Module standby mode (X/Y memory standby enabled)
• One-channel watchdog timer
Rev. 5.00 Dec 12, 2005 page 3 of 1034
REJ09B0254-0500