SH7727 Datasheet, PDF (138/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 2 CPU
Type
Logic
operation
instructions
Shift
instructions
Branch
instructions
Kinds of
Instruction Op Code
6
AND
NOT
OR
TAS
TST
XOR
12
ROTL
ROTR
ROTCL
ROTCR
SHAL
SHAR
SHLL
SHLLn
SHLR
SHLRn
SHAD
SHLD
9
BF
BT
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
Function
Logical AND
Bit inversion
Logical OR
Memory test and bit setting
Logical AND and T bit setting
Exclusive logical OR
1-bit left shift
1-bit right shift
1-bit left shift with T bit
1-bit right shift with T bit
Arithmetic 1-bit left shift
Arithmetic 1-bit right shift
Logical 1-bit left shift
Logical n-bit left shift
Logical 1-bit right shift
Logical n-bit right shift
Arithmetic dynamic shift
Logical dynamic shift
Conditional branch, delayed conditional
branch (T = 0)
Conditional branch, delayed conditional
branch (T = 1)
Unconditional branch
Unconditional branch
Branch to subroutine procedure
Branch to subroutine procedure
Unconditional branch
Branch to subroutine procedure
Return from subroutine procedure
Number of
Instructions
14
16
11
Rev. 5.00 Dec 12, 2005 page 66 of 1034
REJ09B0254-0500