SH7727 Datasheet, PDF (308/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 9 Power-Down Modes and Software Reset
9.2 Register Description
9.2.1 Standby Control Register (STBCR)
The standby control register (STBCR) is an 8-bit readable/writable register that sets the power-
down mode. STBCR is initialized to H'00 by a power-on reset.
Bit: 7
6
STBY
—
Initial value: 0
0
R/W: R/W
R
5
4
3
2
1
0
— STBXTL — MSTP2 MSTP1 MSTP0
0
0
0
0
0
0
R
R/W
R
R/W
R/W
R/W
Bit 7—Standby (STBY): Specifies transition to standby mode.
Bit 7: STBY
0
1
Description
Executing SLEEP instruction puts the chip into sleep mode. (Initial value)
Executing SLEEP instruction puts the chip into standby mode.
Bits 6, 5, and 3—Reserved: These bits are always read as 0. The write value should always as 0.
Bit 4—Standby Crystal (STBXTL): Enables/disables crystal oscillation in standby mode.
Bit 4: STBXTL
0
1
Description
Crystal oscillation in standby mode disabled
Crystal oscillation in standby mode enabled
(Initial value)
Bit 2—Module Stop 2 (MSTP2): Specifies halting the clock supply to the timer unit (TMU) in
the on-chip supporting module. When the MSTP2 bit is set to 1, the clock supply to the TMU is
halted.
Bit 2: MSTP2
0
1
Description
TMU runs.
Clock supply to TMU is halted.
(Initial value)
Rev. 5.00 Dec 12, 2005 page 236 of 1034
REJ09B0254-0500