SH7727 Datasheet, PDF (716/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
(4) Receiving in Slave
Figure 20.12 shows an example of receiving and operation in slave.
No.
Time chart
Start
1
Settting of SIMDR register,
SIMCR register, SITDAR register,
SIRDAR register, SICDAR register,
SIFCTR register
2 "1" is set to TXE bit of SICTR register
Synchronized to SIOFSYNC store receive
3 _{data from RXD_SIO to SIRDR}
Setting content of SIOF
SIOF operation
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
Set the receive enable
Receiving enable when
frame synchronized signal
receive
Receive request is
submitted by receive
FIFO limit
N
4
RDREQ = 1?
Y
5 Reading of SIRDR register
Receive
Reading of receive data
N
Finish to transmit?
6
Y
"0" is set to RXE bit of SICTR register
Set to receive disable
Finish to receive
End
Figure 20.12 Example of Receive Operation in Slave
Rev. 5.00 Dec 12, 2005 page 644 of 1034
REJ09B0254-0500