SH7727 Datasheet, PDF (723/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
(7) A Case of bits Monaural (No. 2)
Sync pulse method, falling edge sampling and secondary FS are requested, Lch. data is assigned to
slot No. 0, control ch. data 0 are assigned to slot No. 0, and frame length is 128 bits.
(a) When the control ch. is not transferred
1 frame
SCK_SIO
SIOFSYN
TXD_SIO
RXD_SIO
Lch. DATA
Slot No. 0 Slot No. 1 Slot No. 2 Slot No. 3 Slot No. 4 Slot No. 5 Slot No. 6 Slot No. 7
1 bit delay
LSB = “0” (secondary FS request)
(b) When the control ch. is transferred
1/2 frame
1 frame
1/2 frame
SCK_SIO
SIOFSYN
TXD_SIO
RXD_SIO
Normal FS
Secondary FS
Normal FS
Lch. DATA
Control ch.0
Slot No.0 Slot No.1 Slot No.2 Slot No.3 Slot No.0 Slot No.1 Slot No.2 Slot No.3
1 bit delay
LSB = “1” (secondary FS request)
Setting: TRMD = 01
TDLE = 1,
RDLE = 1,
CD0E = 1,
REDG = 0,
TDLA3 to TDLA0 = 0000,
RDLA3 to RDLA0 = 0000,
CD0A3 to CD0A0 = 0000,
FL = 1110 (frame length 128 bits),
TDRE = 0, TDRA3 to TDRA0 = 0000,
RDRE = 0, RDRA3 to RDRA0 = 0000,
CD1E = 0, CD1A3 to CD1A0 = 0000
Figure 20.19 Transmit or Receive Timing (16 bits monaural—2)
Rev. 5.00 Dec 12, 2005 page 651 of 1034
REJ09B0254-0500