SH7727 Datasheet, PDF (306/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 9 Power-Down Modes and Software Reset
Table 9.1 Power-Down Modes
State
Mode
Transition
Conditions
CPG CPU
On-Chip
CPU
On-Chip Supporting
Register Memory Modules Pins
External Canceling
Memory Procedure
Sleep
mode
Standby
mode
Module
standby
function
Execute
Runs Halts
SLEEP
instruction
with STBY bit
cleared to 0
in STBCR^*7
Execute
Halts
SLEEP
instruction
with STBY bit
set to 1 in
STBCR^{*4 *5}
Halts
Set MSTP bit Runs Runs
of STBCR
to 1^*6
or
halts
Held
Held
Held
Hardware Drive CA pin Halts Halts Held
standby low
mode
Held
Held
Held
Held
Run
Held Refresh 1. Interrupt
2. Reset
Halt^*1
Held
Self-
refresh
1. Interrupt
2. Reset
Specified ^*2
module halts
Halt^*3
Held
Refresh
Self-
refresh
1. Clear
MSTP bit
to 0
2. Reset
Power-on
reset
Notes: 1. The RTC runs if the START bit in RCR2 is set to 1 (see section 16, Realtime Clock
(RTC)). TMU runs when output of the RTC is used as input to its counter (see section
15, Timer (TMU)).
2. Depends on the on-chip supporting module.
TMU external pin: Held
SCI external pin: Reset
3. The RTC runs if the START bit in RCR2 is set to 1. TMU does not run.
4. USB and LCDC must be stopped before entering standby mode.
1) To stop LCDC, set 0 to DON bit.
2) To stop the USB Host Controller, set USBRESET bit in the HcControl register.
5. For LCDC, refer to the LPS bit in LDPMMR to confirm that power-off sequence has
been completed before entering standby-mode.
6. When putting the RTC into module standby mode, first access one or more of registers
RTC, SCI, and TMU. Then put the RTC into module standby mode.
7. Do not cause the CPU to transition to sleep mode, or cancel sleep mode, during a
transmit or receive operation in which the USB function controller or SIOF uses DMA.
Rev. 5.00 Dec 12, 2005 page 234 of 1034
REJ09B0254-0500