SH7727 Datasheet, PDF (25/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

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933 Table 32.5 Clock Timing (1)
Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.6 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C,
external bus maximum operating frequency = 33 MHz
Item
EXTAL clock input frequency
EXTAL clock input cycle time
EXTAL clock input low pulse width
EXTAL clock input high pulse width
EXTAL clock input rise time
EXTAL clock input fall time
CKIO clock input frequency
CKIO clock input cycle time
CKIO clock input low pulse width
CKIO clock input high pulse width
CKIO clock input rise time
CKIO clock input fall time
CKIO clock output frequency
CKIO clock output cycle time
Symbol
fEX
tEXcyc
tEXL
tEXH
tEXR
tEXF
fCKI
tCKIcyc
tCKIL
tCKIH
tCKIR
tCKIF
fOP
tcyc
Min
6
30.3
7
7
—
—
24
30.3
7
7
—
—
24
30.3
Max
33
167
—
—
6
6
33
40
—
—
6
6
33
40
Unit
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
MHz
ns
Figure
32.1
32.2
32.3
934
Table 32.5 Clock Timing (2)
Conditions: VccQ = 3.0 to 3.6 V, Vcc = 1.75 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C,
external bus maximum operating frequency = 66.67 MHz
Item
Symbol Min
Max Unit Figure
EXTAL clock input frequency
fEX
6
66.67 MHz 32.1
EXTAL clock input cycle time
EXTAL clock input low pulse width
tEXcyc
15.2 167
ns
t EXL
1.5
—
ns
EXTAL clock input high pulse width
tEXH
1.5
—
ns
CKIO clock input frequency
fCKI
24
66.67 MHz 32.2
CKIO clock input cycle time
tCKIcyc
15.2 40
ns
CKIO clock input low pulse width
tCKIL
1.5
—
ns
CKIO clock input high pulse width
tCKIH
1.5
—
ns
CKIO clock output frequency
fOP
24
66.67 MHz 32.3
CKIO clock output cycle time
tcyc
15.2 —
ns
Power-on oscillation settling time
tOSC1
10
—
ns
32.4
935
936
938 Figure 32.3 CKIO Clock Output Timing
t_CK2D
t_CK2D
Revised Version
Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C,
100 MHz products
Item
EXTAL clock input frequency
EXTAL clock input cycle time
EXTAL clock input low pulse width
EXTAL clock input high pulse width
EXTAL clock input rise time
EXTAL clock input fall time
CKIO clock input frequency
CKIO clock input cycle time
CKIO clock input low pulse width
CKIO clock input high pulse width
CKIO clock input rise time
CKIO clock input fall time
CKIO clock output frequency
CKIO clock output cycle time
Symbol
fEX
tEXcyc
tEXL
tEXH
tEXR
tEXF
fCKI
tCKIcyc
tCKIL
tCKIH
tCKIR
tCKIF
fOP
tcyc
Min
6
30
9
9
—
—
24
30
9
9
—
—
24
30
Max
33.34
166.7
—
—
6
6
33.34
41.7
—
—
6
6
33.34
41.7
Unit
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
MHz
ns
Figure
32.3
32.4
32.5
Table 32.6 Clock Timing (2)
Conditions: VccQ = 3.0 to 3.6 V, Vcc = 1.70 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C,
100 MHz products
Item
Symbol Min
Max Unit Figure
EXTAL clock input frequency
fEX
6
50
MHz 32.3
EXTAL clock input cycle time
EXTAL clock input low pulse width
tEXcyc
20
t EXL
4
166.7 ns
—
ns
EXTAL clock input high pulse width
tEXH
4
—
ns
CKIO clock input frequency
fCKI
24
50
MHz 32.4
CKIO clock input cycle time
tCKIcyc
20
41.7 ns
CKIO clock input low pulse width
tCKIL
4
—
ns
CKIO clock input high pulse width
tCKIH
4
—
ns
CKIO clock output frequency
fOP
24
50
MHz 32.5
CKIO clock output cycle time
tcyc
20
41.7 ns
Power-on oscillation settling time
tOSC1
10
—
ms
32.6
Table 32.7 Clock Timing (3)
Newly added
Table 32.8 Clock Timing (4)
Newly added
Figure 32.5 CKIO Clock Output Timing
t_CK2D
t_CK2D
CKIO2
(output)
V_IH
CKIO2
(output)
t_CK2OF
t_CK2OR
V_OH V_OH
V_OL
V_OL
t_CK2OF
V_OH
t_CK2OR
Rev. 5.00 Dec 12, 2005 page xxv of lxxii