SH7727 Datasheet, PDF (352/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 11 Extend Clock Pulse Generator for USB (EXCPG)
11.2.2 Pin Configuration
Table 11.1 shows a pin configuration of the EXCPG.
Table 11.1 Pin Configuration
Pin Name
Abbreviation
External clock pin
UCLK
Note: UCLK is multiplexed with PTD6.
I/O
Input
Description
USB clock input pin (48-MHz input)
11.2.3 Register Configuration
The EXCPG has the internal registers shown in table 11.2.
Table 11.2 Register Configuration
Name
EXCPG control register
Abbreviation R/W
EXCPGCR
W
Initial Value Address
Access Size
H’00
H'A4000236 8
11.3 Register Descriptions
11.3.1 EXCPG Control Register (EXCPGCR)
The EXCPG control register (EXCPGCR) selects the source clock and division ratio for
generation of the EXCPG clock.
EXCPGR is initialized to H'00 by a power-on reset.
Bit:
7
—
Initial value:
0
R/W:
R
6
5
4
3
2
1
0
— USBCKS USBCKS USBCKS USBDIVS USBDIVS USBDIVS
EL2
EL1
EL0
EL2
EL1
EL0
0
0
0
0
0
0
0
R
W
W
W
W
W
W
Bits 7 and 6—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 5.00 Dec 12, 2005 page 280 of 1034
REJ09B0254-0500