SH7727 Datasheet, PDF (742/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 21 Analog Front End Interface (AFEIF)
21.2.6 Ringing Pulse Counter (RCNT)
The result of counting 1 cycle of ringing wave form with AFE_FS is shown here.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RCNT
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bits 15 to 0—Ringing Counter Value (RCNTV): The result of counting 1 cycle of input ringing
wave form with AFE_FS (output of AFE). See section 21.3.3, DAA Interface for more detail
about the ringing detect sequence.
21.2.7 AFE Control Data Register (ACDR)
ACDR is the register to store the AFE control word. After 1 is written to HC bit (ACTR1), data is
transferred to AFE at the timing of 3rd FS.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACDR
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
21.2.8 AFE Status Data Register (ASDR)
ASDR is the register to store the AFE status word. After 1 is written to HC bit (ACTR2), data is
transferred to ASDR from AFE at the timing of 3rd FS.
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASDR
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Rev. 5.00 Dec 12, 2005 page 670 of 1034
REJ09B0254-0500