SH7727 Datasheet, PDF (383/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
12.2.8 Refresh Timer Control/Status Register (RTCSR)
The refresh timer control/status register (RTCSR) is a 16-bit read/write register that specifies the
refresh cycle, whether to generate an interrupt, and that interrupt's cycle. It is initialized to H'0000
by a power-on reset, but is not initialized by a manual reset or standby mode. Before specifying
the CKS2 to CKS0 of RTCST, the RTCOR must be specified.
Note:
Writing to the RTCSR differs from that to general registers to ensure the RTCSR is not
rewritten incorrectly. Use the word-transfer instruction to set the upper byte as
B'10100101 and the lower byte as the write data. For details, see section 12.2.12, Cautions
on Accessing Refresh Control Related Registers.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — — CMF CMIE CKS2 CKS1 CKS0 OVF OVIE LMTS
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—Compare Match Flag (CMF): The CMF status flag indicates that the values of RTCNT
and RTCOR match.
Bit 7: CMF
Description
0
The values of RTCNT and RTCOR do not match.
Clear condition: When a refresh is performed After 0 has been written in
CMF and RFSH = 1 and RMODE = 0 (to perform a CBR refresh).
(Initial value)
1
The values of RTCNT and RTCOR match.
Set condition: RTCNT = RTCOR*
Note: * Contents do not change when 1 is written to CMF.
Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables an interrupt request
caused when the CMF of RTCSR is set to 1. Do not set this bit to 1 when using CAS-before-RAS
refresh or auto-refresh.
Bit 6: CMIE
0
1
Description
Disables an interrupt request caused by CMF
Enables an interrupt request caused by CMF
(Initial value)
Rev. 5.00 Dec 12, 2005 page 311 of 1034
REJ09B0254-0500