SH7727 Datasheet, PDF (232/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 5 Cache
5.5 Usage Examples
5.5.1 Invalidating Specific Entries
Specific cache entries can be invalidated by writing 0 to the entry’s V bit. When the A bit is 1, the
address tag specified by the write data is compared to the address tag within the cache selected by
the entry address, and data is written when a match is found. If no match is found, there is no
operation. R0 specifies the write data in R0 and R1 specifies the address. When the V bit of an
entry in the address array is set to 0, the entry is written back if the entry’s U bit is 1.
; R0=H'01100010; VPN=B'0000 0001 0001 0000 0000 00, U=0, V=0
; R1=H'F0000088; address array access, entry=B'00001000, A=1
;
MOV.L R0,@R1
5.5.2 Reading the Data of a Specific Entry
This example reads the data section of a specific cache entry. The longword indicated in the data
field of the data array in figure 5.6 is read to the register. R0 specifies the address and R1 is read.
; R1=H'F100 004C; data array access, entry=B'00000100, Way = 0,
; longword address = 3
;
MOV.L @R0,R1 ; Longword 3 is read.
Rev. 5.00 Dec 12, 2005 page 160 of 1034
REJ09B0254-0500