SH7727 Datasheet, PDF (451/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Section 14 Direct Memory Access Controller (DMAC)
14.1 Overview
This chip includes a four-channel direct memory access controller (DMAC). The DMAC can be
used in place of the CPU to perform high-speed transfers between external devices that have
DACK (transfer request acknowledge signal), external memory, memory-mapped external
devices, and on-chip supporting modules (SIOF, SCIF, USB function, and A/D converter). Using
the DMAC reduces the burden on the CPU and increases overall operating efficiency.
14.1.1 Features
The DMAC has the following features.
• Four channels
• 4-GB physical address space
• Selectable data transfer length: 8-bit, 16-bit, 32-bit, or 16-byte transfer (In 16-byte transfer,
four 32-bit reads are executed, followed by four 32-bit writes.)
• Maximum of 16 M times of transfers (16777216 times)
• Address mode: Dual address mode and single address mode are supported. In addition, direct
address transfer mode or indirect address transfer mode can be selected.
 Dual address mode transfer: Both the transfer source and transfer destination are accessed
by address. Dual address mode has direct address transfer mode and indirect address
transfer mode.
Direct address transfer mode: The values specified in the DMAC registers indicates the
transfer source and transfer destination. Two bus cycles are required for one data transfer.
Indirect address transfer mode: Data is transferred with the address stored prior to the
address specified in the transfer source address in the DMAC. Other operations are the
same as those of direct address transfer mode. This function is only valid in channel 3.
Four bus cycles are requested for one data transfer.
 Single address mode transfer: Either the transfer source or transfer destination peripheral
device is accessed (selected) by means of the DACK signal, and the other device is
accessed by address. One transfer unit of data is transferred in one bus cycle.
• Channel functions: Transfer mode that can be specified is different in each channel.
 Channel 0: Can accept requests from peripheral modules and external requests.
 Channel 1: Can accept requests from peripheral modules.
 Channel 2: Can accept requests from peripheral modules. This channel has a source address
reload function, which reloads a source address for each 4 transfers.
Rev. 5.00 Dec 12, 2005 page 379 of 1034
REJ09B0254-0500