SH7727 Datasheet, PDF (460/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Bit 20—Direct/Indirect Selection (DI): DI selects direct address mode operation or indirect
address mode operation for a channel 3 source address.
This bit is only valid in CHCR3. This bit in CHCR0 to CHCR2 is always read as 0 and should
only be written with 0.
When using 16-byte transfer, direct address mode must be specified. Operation is not guaranteed if
indirect address mode is specified.
Bit 20: DI
0
1
Description
Direct address mode
Indirect address mode
(Initial value)
Bit 19—Source Address Reload (RO): RO selects whether the source address initial value is
reloaded in channel 2.
This bit is only valid in CHCR2. This bit in CHCR0, CHCR1, and CHCR3 is always read as 0
and should only be written with 0.
When using 16-byte transfer, this bit must be cleared to 0, specifying non-reloading. Operation is
not guaranteed if reloading is specified.
Bit 19: RO
0
1
Description
A source address is not reloaded
A source address is reloaded
(Initial value)
Bit 18—Request Check Level (RL): RL specifies the DRAK (acknowledge of DREQ) signal
output is high active or low active.
This bit is only valid in CHCR0. This bit in CHCR1, CHCR2 and CHCR3 is always read as 0 and
should only be written with 0.
Bit 18: RL
0
1
Description
Low-active output of DRAK
High-active output of DRAK
(Initial value)
Rev. 5.00 Dec 12, 2005 page 388 of 1034
REJ09B0254-0500