SH7727 Datasheet, PDF (93/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 2 CPU
Section 2 CPU
2.1 Registers
The SH7727 has the same registers as in SH-3. In addition, the SH7727 also support the same
DSP-related registers seen in SH-DSP. The basic software-accessible registers are divided into
four distinct groups:
• General-purpose registers
• Control registers
• System registers
• DSP registers
With the exception of a number of DSP registers, all of these registers are 32-bit width. The
general-purpose registers are accessible from the user mode, with R0 to R7 banked to provide each
processor mode access to a separate set of the R0 to R7 registers (i.e. R0 to R7_BANK0, and R0
to R7_BANK1). In the privileged mode, the register bank (RB) bit in the status register (SR)
defines which set of banked registers (R0 to R7_BANK0 or R0 to R7_BANK1) is accessed as
general-purpose registers, and which are accessed only by the LDC/STC instructions.
The control registers can be accessed by the LDC/STC instructions. The GBR, RS, RE, and MOD
registers can also be accessed in user mode. Control registers are:
• SR: Status register
• SSR: Saved status register
• SPC: Saved program counter
• GBR: Global base register
• VBR: Vector base register
• RS: Repeat start register (DSP mode only)
• RE: Repeat end register (DSP mode only)
• MOD: Modulo register (DSP mode only)
The system registers are accessed by the LDS/STS instructions (the PC cannot be accessed by
software, but is included here because its contents are saved in, and restored from, SPC). The
system registers are:
• MACH: Multiply and accumulate high register
• MACL: Multiply and accumulate low register
• PR: Procedure register
Rev. 5.00 Dec 12, 2005 page 21 of 1034
REJ09B0254-0500