SH7727 Datasheet, PDF (668/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
• Serial data reception
Figures 19.8 and 19.9 show sample serial reception flowcharts. After SCIF reception is enabled,
use the following procedure to perform serial data reception.
Start reception
Read DR, ER, BRK
flags in SCSSR2
BRK v ER v DR = 1?
(1)
Yes
(1) Receive error handling and break
detection:
Read the DR, ER, and BRK flags in
SCSSR2 to identify any error, perform
the appropriate error handling, then
clear the DR, ER, and BRK flags to 0.
In the case of a framing error, a break
can also be detected by reading the
value of the RxD2 pin.
No
Error processing
(2) SCIF status check and receive data
Read RDF flag in SCSSR2
(2)
read :
Read the serial status register 2
(SCSSR2) and check that RDF = 1,
No
RDF = 1?
then read the receive data in the
receive FIFO data register 2
(SCFRDR2), read 1 from the RDF flag,
Yes
and then clear the RDF flag to 0. The
transition of the RDF flag from 0 to 1
Read receive data in SCFRDR2,
and clear RDF flag in
(3)
SCSSR2 to 0
can be identified by an RXI interrupt.
(3) Serial reception continuation
procedure:
To continue serial reception, read at
No
All data received?
least the receive trigger set number of
receive data bytes from SCFRDR2,
read 1 from the RDF flag, then clear the
RDF flag to 0. The number of receive
Yes
data bytes in SCFRDR2 can be
Clear RE bit in SCSCR2 to 0
ascertained by reading the lower bits of
SCFDR2.
End reception
Figure 19.8 Sample Serial Reception Flowchart (1)
Rev. 5.00 Dec 12, 2005 page 596 of 1034
REJ09B0254-0500