SH7727 Datasheet, PDF (478/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
(1) Direct address transfer mode
DMA transfer requires two bus cycles because data is read from the transfer source in a data
read cycle and written to the transfer destination in a data write cycle. At this time, transfer
data is temporarily stored in the DMAC. In the transfer between external memories as shown
in figure 14.5, data is read from one external memory to the DMAC in a data read cycle, and
then that data is written to the other external memory in a write cycle. Figures 14.6 to 14.8
show examples of this operation timing
DMAC
SAR
DAR
Memory
Transfer source
module
Data buffer
Transfer destination
module
Data is read from the transfer source module using the SAR value as
the address, and the read data is stored in the DMAC temporarily.
DMAC
First bus cycle
SAR
Memory
DAR
Transfer source
module
Data buffer
Transfer destination
module
The value stored in the DMAC is written to the transfer destination
module using the DAR value as the address.
Second bus cycle
Figure 14.5 Operation in Direct Address Mode
Rev. 5.00 Dec 12, 2005 page 406 of 1034
REJ09B0254-0500