SH7727 Datasheet, PDF (309/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 9 Power-Down Modes and Software Reset
Bit 1—Module Stop 1 (MSTP1): Specifies halting the clock supply to the realtime clock (RTC)
in the on-chip supporting module. When the MSTP1 bit is set to 1, the clock supply to RTC is
halted. When the clock halts, all RTC registers cannot be accessed, but the counter keeps running.
Bit 1: MSTP1
0
1
Description
RTC runs.
Clock supply to RTC is halted.
(Initial value)
Bit 0—Module Stop 0 (MSTP0): Specifies halting the clock supply to the serial communication
interface (SCI) in the on-chip supporting module. When the MSTP0 bit is set to 1, the clock
supply to the SCI is halted.
Bit 0: MSTP0
0
1
Description
SCI runs.
Clock supply to SCI is halted.
(Initial value)
9.2.2 Standby Control Register 2 (STBCR2)
The standby control register 2 (STBCR2) is an 8-bit readable/writable register that controls the
operation of the peripheral modules in the normal mode and sleep mode. STBCR is initialized to
H'00 by a power-on reset.
Bit: 7
6
5
4
3
2
1
0
MSTP9 MDCHG MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 —
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W
R
Bit 7— Module Stop 9 (MSTP9): Specifies halting the clock supply to the X/Y memory. When
the MSTP9 bit is set to 1, the clock supply to the X/Y memory is halted. Halting of the clock
supply to the X/Y memory must be controlled by software (any access is not blocked by
hardware).
Bit 7: MSTP9
0
1
Description
X/Y memory runs
Clock supply to X/Y memory is halted
(Initial value)
Rev. 5.00 Dec 12, 2005 page 237 of 1034
REJ09B0254-0500