SH7727 Datasheet, PDF (455/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Channel Name
Abbrevi-
Initial
ation
R/W Value
Address
Register Access
Size
Size
2
3
Shared
DMA source address
register 2
SAR2
R/W Undefined H'04000040
32 bits
(H'A4000040)^*4
DMA destination address DAR2
register 2
R/W Undefined H'04000044
32 bits
(H'A4000044)^*4
DMA transfer count
register 2
DMA channel control
register 2
DMATCR2
CHCR2
R/W
R/W^*1
Undefined H'04000048
24 bits
(H'A4000048)^*4
H'00000000 H'0400004C 32 bits
(H'A400004C)^*4
DMA source address
register 3
SAR3
R/W Undefined H'04000050
32 bits
(H'A4000050)^*4
DMA destination address DAR3
register 3
R/W Undefined H'04000054
32 bits
(H'A4000054)^*4
DMA transfer count
register 3
DMA channel control
register 3
DMA operation register
DMATCR3 R/W
Undefined H'04000058
24 bits
(H'A4000058)^*4
CHCR3
R/W^*1 H'00000000 H'0400005C
32 bits
(H'A400005C)^*4
DMAOR R/W^*1 H'0000
H'04000060
16 bits
(H'A4000060)^*4
16, 32^*2
16, 32^*2
16, 32^*3
8, 16,
32^*2
16, 32^*2
16, 32^*2
16, 32^*3
8, 16,
32^*2
8, 16^*2
DMA channel assign
register
CHRAR R/W H’0000
H’0400022A 16 bits 16
(H’A400022A)^*4
Notes: These registers are located in area 1 of physical space. Therefore, when the cache is on,
either access these registers from the P2 area of logical space or else make an appropriate
setting using the MMU so that these registers are not cached.
1. Only a write of 0 after a read of 1 to clear a flag is enabled for bit 1 in CHCR0 to
CHCR3 and bits 1 and 2 in DMAOR.
2. If SAR0 to SAR3, DAR0 to DAR3, and CHCR0 to CHCR3 are accessed in 16 bits, the
16 bit values that were not accessed are held.
3. DMATCR comprises the 24 bits from bit 0 to bit 23. The upper 8 bits, bits 24 to 31,
cannot be written with 1 and are always read as 0.
4. When address translation by the MMU does not apply, the address in parentheses
should be used.
Rev. 5.00 Dec 12, 2005 page 383 of 1034
REJ09B0254-0500