SH7727 Datasheet, PDF (511/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
The state in the DMAC differ depending on the address reload function setting as shown in table
14.9.
Table 14.9 DMAC Sate after the Fourth Transfer Ends
Items
Address Reload On
Address Reload Off
SAR
H'04000080
H'04000090
DAR
H'003FFFFC
H'003FFFFC
DMATCR
H'0000007C
H'0000007C
Bus right
Released
Held
DMAC operation
Stops
Continues operating
Interrupt
Not generated
Not generated
Transfer request source flag
clear
Executed
Not executed
Notes: 1. When the value in DMATCR reaches 0 and the IE bit in CHCR has been set to 1,
interrupts are generated regardless of the address reload function setting.
2. When the value in DMATCR reaches 0, the transfer request source flag is cleared
regardless of the address reload function setting.
3. Specify the burst mode when using the address reload function. This function may not
be correctly executed in the cycle steal mode.
4. Set the DMATCR value to a multiple of four when using the address reload function.
This function may not be correctly executed if other values are specified.
14.5.2 Example of DMA Transfer between External Memory and SCIF Transmitter
(Indirect Address on)
In this example, DMA transfer is performed between the external memory specified with the
indirect address (transfer source) and the SCIF transmitter (transfer destination) using DMAC
channel 3. Table 14.10 shows the transfer conditions and register settings. In addition, it is
recommendable that the trigger for the number of transmit FIFO data is set to 1 (TTRG1 = TTRG0
= 1 in SCFCR).
Rev. 5.00 Dec 12, 2005 page 439 of 1034
REJ09B0254-0500