SH7727 Datasheet, PDF (8/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

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169 7.2.2 IRQ Interrupt
IRQ interrupts are input by priority from pins
IRQ0 to IRQ5 with a level or an edge. The
priority level can be set by priority setting
registers C, D (IPRC, IPRD) in a range from
levels 0 to 15.
IRQ interrupts are input by priority from pins
IRQ0 to IRQ5 with a level or an edge. The
priority level can be set by priority setting
registers C, D (IPRC, IPRD) in a range from
levels 0 to 15.
When using edge-sensing for IRQ
interrupts, clear the interrupt source by
having software read 1 from the
corresponding bit in IRR0, then write 0 to
the bit.
When using edge sensing for IRQ
interrupts, do the following to clear IR0.
To clear bits IRQ5R to IRQ0R to 0, read
from IRR0 before writing. After confirming
that the bits to be cleared to 0 are set to 1,
write 0 to them. In this case write 0 only to
the bits to be cleared; write 1 to the other
bits. The values of the bits to which 1 is
written do not change.
When level sensing is used for IRQ
interrupts, bits IRQ5R to IRQ0R indicate
whether or not an interrupt request has
been input. They can be set and cleared by
the values input to pins IRQ5R to IRQ0R
alone.
175 Table 7.4 Interrupt Exception Handling
Sources and Priority (IRQ Mode)
Interrupt Source
TMU1 TUNI1
TMU2 TUNI2
TICPI2
RTC
ATI
PRI
CUI
SCI0 ERI
RXI
TXI
TEI
INTEVT Code
(INTEVT2 Code)
H'420 (H'420)
H'440 (H'440)
H'460 (H'460)
H'480 (H'480)
H'4A0 (H'4A0)
H'4C0 (H'4C0)
H'4E0 (H'4E0)
H'500 (H'500)
H'520 (H'520)
H'540 (H'540)
Interrupt
Priority
IPR (Bit
(Initial Value) Numbers)
0–15 (0)
IPRA (11–8)
0–15 (0)
IPRA (7–4)
0–15 (0)
IPRA (3–0)
Priority
within IPR
Setting Default
Unit
Priority
—
High
High
Low
High
0–15 (0)
IPRB (3–0)
Low
High
Low
Low
Interrupt Source
TMU1 TUNI1
TMU2 TUNI2
RTC
ATI
PRI
CUI
SCI0 ERI
RXI
TXI
TEI
INTEVT Code
(INTEVT2 Code)
H'420 (H'420)
H'440 (H'440)
H'480 (H'480)
H'4A0 (H'4A0)
H'4C0 (H'4C0)
H'4E0 (H'4E0)
H'500 (H'500)
H'520 (H'520)
H'540 (H'540)
Interrupt
Priority
IPR (Bit
(Initial Value) Numbers)
0–15 (0)
IPRA (11–8)
0–15 (0)
IPRA (7–4)
0–15 (0)
IPRA (3–0)
Priority
within IPR
Setting Default
Unit
Priority
—
High
—
High
0–15 (0)
IPRB (7–4)
Low
High
Low
Low
177
Table 7.5 Interrupt Exception Handling
Sources and Priority (IRL Mode)
Interrupt Source
ADC ADI
LCDC LCDCI
TMU1 TUNI1
TMU2 TUNI2
TICPI2
INTEVT Code
(INTEVT2 Code)
Interrupt
Priority
(Initial IPR (Bit
Value) Numbers)
H'200–3C0* (H'980) 0–15 (0) IPRE (3–0)
H'200–3C0* (H'9A0) 0–15 (0) IPRF (11–8)
H'420 (H'420)
0–15 (0) IPRA (11–8)
H'440 (H'440)
0–15 (0) IPRA (7–4)
H'460 (H'460)
Priority
within IPR
Setting Default
Unit
Priority
—
High
—
—
High
Low
Low
Interrupt Source
ADC ADI
LCDC LCDCI
TMU1 TUNI1
TMU2 TUNI2
INTEVT Code
(INTEVT2 Code)
Interrupt
Priority
(Initial IPR (Bit
Value) Numbers)
H'200–3C0* (H'980) 0–15 (0) IPRE (3–0)
H'200–3C0* (H'9A0) 0–15 (0) IPRF (11–8)
H'420 (H'420)
0–15 (0) IPRA (11–8)
H'440 (H'440)
0–15 (0) IPRA (7–4)
Priority
within IPR
Setting Default
Unit
Priority
—
High
—
—
—
Low
Rev. 5.00 Dec 12, 2005 page viii of lxxii