SH7727 Datasheet, PDF (810/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 24 USB HOST Module
Register: HcInterruptEnable
Bits
Reset
R/W
31
0b
R/W
30
0b
R/W
29–7
0h
—
6
0b
R/W
5
0b
R/W
4
0b
R/W
3
0b
R/W
2
0b
R/W
1
0b
R/W
0
0b
R/W
Offset: 10–13
Description
MasterInterruptEnable (MIE)
Setting of this bit to 0 is ignored by the host controller. When
this bit is set to 1, an interrupt generation by the event specified
in another bit in this register is enabled. This is used by HDC
that the master interrupt is enabled. When an interrupt is
detected by HCD, use the USBIH bit of Interrupt Controller
INTC.
0: Ignore (initial value)
1: Enable interrupt generation due to the specified event.
OwnershipChangeEnable (OC)
0: Ignore (initial value)
1: Enable interrupt generation due to Ownership Change.
Reserved.
RootHubStatusChangeEnable (RHSC)
0: Ignore (initial value)
1: Enable interrupt generation due to Root Hub Status Change.
FrameNumberOverflowEnable (FNO)
0: Ignore (initial value)
1: Enable interrupt generation due to Frame Number Overflow.
UnrecoverableErrorEnable(UE)
0: Ignore (initial value)
1: Enable interrupt generation due to unrecoverable error.
ResumeDetectedEnable (RD)
0: Ignore (initial value)
1: Enable interrupt generation due to Resume Detected.
StartOfFrameEnable (SF)
0: Ignore (initial value)
1: Enable interrupt generation due to Start of Frame.
WritebackDoneHeadEnable (WDH)
0: Ignore (initial value)
1: Enable interrupt generation due to Writeback Done Head.
SchedulingOverrunEnable (SO)
0: Ignore (initial value)
1: Enable interrupt generation due to Scheduling Overrun.
Rev. 5.00 Dec 12, 2005 page 738 of 1034
REJ09B0254-0500