SH7727 Datasheet, PDF (643/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
19.2.3 Transmit Shift Register 2 (SCTSR2)
The transmit shift register 2 (SCTSR2) transmits serial data. The SCI loads transmit data from the
transmit FIFO data register 2 (SCFTDR2) into the SCTSR2, then transmits the data serially from
the TxD2 pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the
next transmit data from the SCFTDR2 into the SCTSR2 and starts transmitting again. The CPU
cannot read or write the SCTSR2 directly.
Bit: 7
6
5
4
3
2
1
0
R/W: —
—
—
—
—
—
—
—
19.2.4 Transmit FIFO Data Register 2 (SCFTDR2)
The transmit FIFO data register 2 (SCFTDR2) is a 16-byte 8-bit-length FIFO register that stores
data for serial transmission. When the SCIF detects that the transmit shift register (SCTSR2) is
empty, it moves transmit data written in the SCFTDR2 into the SCTSR2 and starts serial
transmission. Continuous serial transmission is performed until the transmit data in the SCFTDR2
becomes empty. The CPU can always write to the SCFTDR2.
When the transmit data in the SCFTDR2 is full (16 bytes), next data cannot be written. If
attempted to write, the data is ignored.
Bit: 7
6
5
4
3
2
1
0
R/W: W
W
W
W
W
W
W
W
Rev. 5.00 Dec 12, 2005 page 571 of 1034
REJ09B0254-0500