SH7727 Datasheet, PDF (1081/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Appendix A Pin Functions
Table A.5 Pin Status (Burst ROM/Little Endian) (cont)
32-Bit Bus Width
Byte
Byte
Byte
Byte
Word
Word
Pin
Access Access Access Access Access Access Longword
(Address (Address (Address (Address (Address (Address Access
4n)
4n+1)
4n+2)
4n+3)
4n)
4n+2)
CS6 to CS2, CS0
Enabled Enabled Enabled Enabled Enabled Enabled Enabled
RD
R Low
Low
Low
Low
Low
Low
Low
W—
—
—
—
—
—
—
RD/WR
R High
High
High
High
High
High
High
W—
—
—
—
—
—
—
BS
Enabled Enabled Enabled Enabled Enabled Enabled Enabled
RAS3
High
High
High
High
High
High
High
CAS
High
High
High
High
High
High
High
WE0/DQMLL
R High
High
High
High
High
High
High
W—
—
—
—
—
—
—
WE1/DQMLU/WE
R High
High
High
High
High
High
High
W—
—
—
—
—
—
—
WE2/DQMUL/ICIORD R High
High
High
High
High
High
High
W—
—
—
—
—
—
—
WE3/DQMUU/ICIOWR R High
High
High
High
High
High
High
W—
—
—
—
—
—
—
CE2A
High
High
High
High
High
High
High
CE2B
High
High
High
High
High
High
High
CKE
WAIT
Disabled Disabled Disabled Disabled Disabled Disabled Disabled
Enabled^*1 Enabled^*1 Enabled^*1 Enabled^*1 Enabled^*1 Enabled^*1 Enabled^*1
IOIS16
Disabled Disabled Disabled Disabled Disabled Disabled Disabled
A25 to A0
Address Address Address Address Address Address Address
D7 to D0
Valid data Invalid
data
Invalid
data
Invalid
data
Valid data Invalid
data
Valid data
D15 to D8
Invalid
data
Valid data Invalid
data
Invalid
data
Valid data Invalid
data
Valid data
D23 to D16
Invalid
data
Invalid
data
Valid data Invalid
data
Invalid
data
Valid data Valid data
D31 to D24
Invalid
data
Invalid
data
Invalid
data
Valid data Invalid
data
Valid data Valid data
Notes: 1. Disabled when the wait setting of the WCR2 register is 0.
2. Unused pins can be switched to port function, pull-up.
Rev. 5.00 Dec 12, 2005 page 1009 of 1034
REJ09B0254-0500