SH7727 Datasheet, PDF (811/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 24 USB HOST Module
24.2.6 HcInterruptDisable
HcInterruptDisable Register (H'04000414)
Each disable bit in the HcInterruptDisable register corresponds to the related interrupt bit in the
HcInterruptStatus register. The HcInterruptDisable register is related to the HcInterruptEnable
register. Therefore, writing a 1 to a bit in this register clears the corresponding bit in
HcInterruptEnable register, while writing a 0 to a bit leaves the corresponding bit in the
HcInterruptEnable register. When read, the current value of the HcInterruptEnable register is
returned.
Register: HcInterruptDisable
Bits
Reset R/W
31
0b
R/W
30
0b
R/W
29–7
0h
—
6
0b
R/W
5
0b
R/W
4
0b
R/W
3
0b
R/W
2
0b
R/W
1
0b
R/W
Offset: 14–17
Description
MasterInterruptEnable (MIE)
0: Ignore
1: Disable interrupt generation due to the specified event.
OwnershipChangeEnable (OC)
0: Ignore
1: Disable interrupt generation due to Ownership Change.
Reserved. Read/Write 0's
RootHubStatusChangeEnable (RHSC)
0: Ignore
1: Disable interrupt generation due to Root Hub Status Change.
FrameNumberOverflowEnable (FNO)
0: Ignore
1: Disable interrupt generation due to Frame Number Overflow.
UnrecoverableErrorEnable (UE)
0: Ignore
1: Disable interrupt generation due to unrecoverable error.
ResumeDetectedEnable (RD)
0: Ignore
1: Disable interrupt generation due to Resume Detected.
StartofFrameEnable (SF)
0: Ignore
1: Disable interrupt generation due to Start of Frame.
WritebackDoneHeadEnable (WDH)
0: Ignore
1: Disable interrupt generation due to Writeback Done Head.
Rev. 5.00 Dec 12, 2005 page 739 of 1034
REJ09B0254-0500