SH7727 Datasheet, PDF (278/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 8 User Break Controller
8.2 Register Descriptions
8.2.1 Break Address Register A (BARA)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA BAA
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BARA is a 32-bit read/write register. BARA specifies the address used as a break condition in
channel A. A power-on reset initializes BARA to H'00000000.
Bits 31 to 0—Break Address A31 to A0 (BAA31 to BAA0): Stores the address on the LAB or
IAB specifying break conditions of channel A.
8.2.2 Break Address Mask Register A (BAMRA)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA BAMA
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BAMRA is a 32-bit read/write register. BAMRA specifies bits masked in the break address
specified by BARA. A power-on reset initializes BAMRA to H'00000000.
Rev. 5.00 Dec 12, 2005 page 206 of 1034
REJ09B0254-0500