SH7727 Datasheet, PDF (224/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 5 Cache
31
6 5 43 21 0
……………………
CF CB WT CE
:
Reserved bits. These bits are always read as 0. The write value should always be 0.
CF:
Cache flush bit. Writing 1 flushes all cache entries (clears the V, U, and LRU bits of all
cache entries to 0). Always reads 0. Write-back to external memory is not performed when
the cache is flushed.
WT: Write-through bit. Indicates the cache's operating mode for areas P0, U0 and P3.
1 = write-through mode, 0 = write-back mode.
CE:
Cache enable bit. Indicates whether the cache function is used.
1 = cache used, 0 = cache not used.
CB:
Cache write-back bit. Indicates the cache's operating mode for area P1.
1 = write-back mode, 0 = write-through mode.
Figure 5.2 CCR Register Configuration
5.2.2 Cache Control Register 2 (CCR2)
CCR2 register is used to enable or disable cache locking mechanism during DSP mode (CPU
status register bit 12) only. Executing a prefetch instruction (PREF) during DSP mode will bring
in one line size of data pointed by Rn to cache, according to the setting of CCR2 [9:8] (W3LOAD,
W3LOCK) and [1:0] (W2LOAD, W2LOCK):
When CCR2[9:8]=11, during DSP mode PREF @Rn will bring the data into way 3. When
CCR2[9:8]=00, 01 or 10 during DSP mode, or any setting during non-DSP mode, PREF @Rn will
place the data into the way pointed by LRU.
When CCR2[1:0]=11, during DSP mode PREF @Rn will bring the data into way 2. When
CCR2[1:0]=00, 01 or 10 during DSP mode, or any setting during non-DSP mode, PREF @Rn will
place the data into the way pointed by LRU.
CCR2 must be set before cache is enabled.
When a PREF instruction is issued and there is a cache hit, the operation is treated as NOP.
Figure 5.3 shows the configuration of the CCR2 register.
The CCR2 register is a write-only register. If read, an undefined value will be returned.
Rev. 5.00 Dec 12, 2005 page 152 of 1034
REJ09B0254-0500