SH7727 Datasheet, PDF (504/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Register Configuration
Table 14.7 summarizes the CMT register configuration.
Table 14.7 Register Configuration
Name
Abbreviation R/W
Initial
Value Address
Access Size
(Bits)
Compare-match timer start
register
Compare-match timer
control/status register 0
CMSTR
CMCSR0
R/(W) H'0000
R/(W)^*1 H'0000
H'04000070 8, 16, 32
(H'A4000070)^*2
H'04000072 8, 16, 32
(H'A4000072)^*2
Compare-match counter 0 CMCNT0
R/W H'0000 H'04000074 8, 16, 32
(H'A4000074)^*2
Compare-match constant
register
CMCOR0
R/W H'FFFF H'04000076 8, 16, 32
(H'A4000076)^*2
Notes: 1. Only a 0 can be written to CMF bits in CMCSR0, to clear the flag.
2. When the address conversion by the MMU is not provided, use the address in
parentheses.
14.4.2 Register Descriptions
Compare-Match Timer Start Register (CMSTR)
The compare-match timer start register (CMSTR) is a 16-bit register that selects whether compare-
match counter 0 (CMCNT0) is operated or halted. CMSTR is initialized to H'0000 by a reset, but
it retains its previous values in standby mode.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
STR0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W
R/W
Bits 15 to 2—Reserved: These bits are always read as 0 and should only be written with 0.
Rev. 5.00 Dec 12, 2005 page 432 of 1034
REJ09B0254-0500