SH7727 Datasheet, PDF (178/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 3 Memory Management Unit (MMU)
31
10 9
0
VPN
Offset
Virtual address (1-kbyte page)
31
12 11
0
VPN
Offset
Virtual address (4-kbyte page)
(15)
(2)
(8) (1) (1) (1)
VPN (31−17) VPN (11−10) ASID SH SZ V
(22)
PPN
(2) (1) (1)
PR C D
Legend:
TLB entry
VPN: Virtual page number. Top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of
virtual address for a 4-kbyte page. Since VPN bits 16 to 12 are used as the index number,
they are not stored in the TLB entry.
ASID: Address space identifier. Indicates the process that can access a virtual page. In single
virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0,
the address is compared with the ASID in PTEH when address comparison is performed.
SH: Share status bit
0 = Page not shared between processes
1 = Page shared between processes
SZ: Page-size bit
0 = 1-kbyte page
1 = 4-kbyte page
V: Valid bit. Indicates whether entry is valid.
0 = Invalid
1 = Valid
Cleared to 0 by a power-on reset. Not affected by a manual reset.
PPN: Physical page number. Top 22 bits of physical address. PPN bits 11 and 10 are not used in
case of a 4-kbyte page. Attention must be paid to the synonym problem in case of a 1-kbyte
page (see section 3.4.4, Avoiding Synonym Problems).
PR: Set the most significant bit to 0.
Protection key field. 2-bit field encoded to define the access rights to the page.
00: Reading only is possible in privileged mode.
01: Reading/writing is possible in privileged mode.
10: Reading only is possible in privileged/user mode.
11: Reading/writing is possible in privileged/user mode.
C: Cacheable bit. Indicates whether the page is cacheable.
0 = Non-cacheable
1 = Cacheable
D: Dirty bit. Indicates whether the page has been written to.
0 = Not written to
1 = Written to
Figure 3.5 Logical Address and TLB Structure
Rev. 5.00 Dec 12, 2005 page 106 of 1034
REJ09B0254-0500