SH7727 Datasheet, PDF (828/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 24 USB HOST Module
Register: HcRhPortStatus[1:2]
Bits
Reset
R/W
1
0
R/W
0
0
R/W
Offset: 54–57, 58–5B
Description
(read) PortEnableStatus (PES)
This bit indicates whether the port is enabled or disabled. The
root hub clears this bit when the over-current condition and a
operational bus error such as disconnect event, power-off
switch, or babble is detected. PortEnabledStatusChange is set
by this change. This bit is set by writing SetPortEnable and
cleared by writing ClearPortEnable. This bit cannot be set when
CurrentConnectStatus is cleared. In addition, this bit is set upon
completion of the port reset by which ResetStatusChange is
set, or uponcompletion of the port suspend by which
SuspendStatusChange is set.
0 = Port disabled. (initial value)
1 = Port enabled.
(write) SetPortEnable
Writing a 1 sets PortEnableStatus. Writing a 0 has no effect.
If CurrentConnectStatus is cleared, this writing does not set
PortEnableStatus, instead, sets ConnectStatusChange. This
reports the driver that the power disconnection port has been
tried to be enabled.
(read) CurrentConnectStatus (CCS)
This bit indicates the status of the downstream port.
0 = No device connected.
1 = Device connected.
Note: If DeviceRemoveable is set (not removable) this bit is
always 1.
(write) ClearPortEnable
Writing a 1 clears PortEnableStatus. Writing a 0 has no effect.
CurrentConnectStatus is not affected by any writing.
Rev. 5.00 Dec 12, 2005 page 756 of 1034
REJ09B0254-0500