SH7727 Datasheet, PDF (785/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

23.6.4 EP1 Bulk-Out Transfer (Dual FIFOs)
USB function
OUT token reception
Section 23 USB Function Controller
Application
Space
in EP1 FIFO?
Yes
No
NACK
Data reception from host
ACK
USBIFR0/EP1 FULL status
bit automatically set to 1
Interrupt request
Read USBEP1 receive-data
size register (USBEPSZ1)
Read data from USBEP1
data register (USBEPDR1)
Write 1 to EP1 read-end bit
(USBTRG/EP1 RDFN = 1)
Both FIFOs
are empty?
No Interrupt request
Yes
USBIFR0/EP1 FULL status
bit automatically cleared to 0
Figure 23.10 EP1 Bulk-Out Transfer Operation
EP1 has two 64-byte FIFOs, but the user can perform data reception and receive-data reads
without being aware of this dual-FIFO configuration.
When one FIFO is full after reception is completed, the USBIFR0/EP1 FULL bit is set. After the
first receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty,
Rev. 5.00 Dec 12, 2005 page 713 of 1034
REJ09B0254-0500