SH7727 Datasheet, PDF (525/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 15 Timer (TMU)
• On-Chip RTC Clock Operation
Select the on-chip RTC clock as the timer clock with the TPSC2 to TPSC0 bits in TCR.
RTC output
clock
TCNT input
clock
TCNT
N+1
N
N−1
Figure 15.5 Count Timing when On-Chip RTC Clock is Operating
15.4 Interrupts
There is only one source for TMU interrupts: underflow interrupts (TUNI).
15.4.1 Status Flag Set Timing
The UNF bit is set to 1 when TCNT underflows. Figure 15.6 shows the timing.
Pφ
TCNT
Underflow
signal
UNF
TUNI
H'00000000
TCOR value
Figure 15.6 UNF Set Timing
Rev. 5.00 Dec 12, 2005 page 453 of 1034
REJ09B0254-0500