SH7727 Datasheet, PDF (54/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Figure 3.13 MMU Exception Signals in Data Access ............................................................... 122
Figure 3.14 MMU Exception in Repeat Loop ........................................................................... 123
Figure 3.15 Specifying Address and Data for Memory-Mapped TLB Access .......................... 126
Section 4 Exception Handling
Figure 4.1 Vector Table........................................................................................................... 132
Figure 4.2 Example of Acceptance Order of General Exceptions ........................................... 135
Figure 4.3 Bit Configurations of EXPEVT, INTEVT, INTEVT2, and TRA Registers........... 139
Section 5 Cache
Figure 5.1 Cache Structure ...................................................................................................... 150
Figure 5.2 CCR Register Configuration .................................................................................. 152
Figure 5.3 CCR2 Register Configuration ................................................................................ 153
Figure 5.4 Cache Search Scheme ............................................................................................ 155
Figure 5.5 Write-Back Buffer Configuration........................................................................... 157
Figure 5.6 Specifying Address and Data for Memory-Mapped Cache Access........................ 159
Section 6 X/Y Memory
Figure 6.1 X/Y Memory Logical Address Mapping................................................................ 163
Figure 6.2 X/Y Memory Physical Address Mapping .............................................................. 164
Section 7 Interrupt Controller (INTC)
Figure 7.1 INTC Block Diagram ............................................................................................. 166
Figure 7.2 Example of IRL Interrupt Connection.................................................................... 171
Figure 7.3 Interrupt Operation Flowchart................................................................................ 198
Figure 7.4 Example of Pipeline Operations when IRL Interrupt is Accepted ......................... 202
Section 8 User Break Controller
Figure 8.1 Block Diagram of User Break Controller............................................................... 204
Section 9 Power-Down Modes and Software Reset
Figure 9.1 Canceling Standby Mode with STBCR.STBY....................................................... 246
Figure 9.2 Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output ........................... 249
Figure 9.3 Manual Reset STATUS Output.............................................................................. 250
Figure 9.4 Standby to Interrupt STATUS Output.................................................................... 250
Figure 9.5 Standby to Power-On Reset STATUS Output........................................................ 251
Figure 9.6 Standby to Manual Reset STATUS Output............................................................ 251
Figure 9.7 Sleep to Interrupt STATUS Output ........................................................................ 252
Figure 9.8 Sleep to Power-On Reset STATUS Output............................................................ 252
Figure 9.9 Sleep to Manual Reset STATUS Output................................................................ 253
Figure 9.10 Hardware Standby Mode Timing (CA = Low in Normal Operation) .................... 255
Rev. 5.00 Dec 12, 2005 page liv of lxxii