SH7727 Datasheet, PDF (974/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 30 PC Card Controller (PCC)
Bit 2—PCC0 Ready Change Enable (P0RE): When the PC card connected to area 6 is on the IC
memory card interface, bit 2 enables or disables the interrupt request when the value of the
RDY/BSY pin is changed. This bit has no meaning on the I/O card interface.
Bit 2: P0RE
0
1
Description
No interrupt occurs for the PC card connected to area 6 regardless of the
value of the RDY/BSY pin
(Initial value)
An interrupt occurs for the PC card connected to area 6 when the value of
the RDY/BSY pin is changed from 0 to 1
Bit 1—PCC0 Battery Warning Enable (P0BWE): When the PC card connected to area 6 is on
the IC memory card interface, bit 1 enables or disables the interrupt request when the BVD2 and
BVD1 pins are in the state in which “the battery must be changed although the data is guaranteed”.
This bit has no meaning on the I/O card interface.
Bit 1: P0BWE
0
1
Description
No interrupt occurs when the BVD2 and BVD1 pins are in the state in which
“the battery must be changed although the data is guaranteed” (Initial value)
An interrupt occurs when the BVD2 and BVD1 pins are in the state in which
“the battery must be changed although the data is guaranteed”
Bit 0—PCC0 Battery Dead Enable (P0BDE): When the PC card connected to area 6 is on the
IC memory card interface, bit 0 enables or disables the interrupt request when the BVD2 and
BVD1 pins are in the state in which “the battery must be changed since the data is not
guaranteed”. This bit has no meaning on the I/O card interface.
Bit 0: P0BDE
0
1
Description
No interrupt occurs when the BVD2 and BVD1 pins are in the state in which
“the battery must be changed since the data is not guaranteed” (Initial value)
An interrupt occurs when the BVD2 and BVD1 pins are in the state in which
“the battery must be changed since the data is not guaranteed”
Rev. 5.00 Dec 12, 2005 page 902 of 1034
REJ09B0254-0500