SH7727 Datasheet, PDF (665/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
• Serial data transmission
Figure 19.5 shows a sample serial transmission flowchart. After SCIF transmission is enabled, use
the following procedure to perform serial data transmission.
Start transmission
Read TDFE bit in SCSSR2
(1)
No
TDFE= 1?
Yes
Write transmit data (16 - transmit
trigger set number) to SCFTDR2,
read 1 from TDFE bit and TEND flag
in SCSSR2, then clear to 0
All data transmitted?
(2)
No
Yes
Read TEND bit in SCSSR2
No
TEND= 1?
Yes (3)
No
Break output?
Yes
Set SCPDR2 and SCPCR2
(1) SCIF status check and transmit data write:
Read serial status register 2 (SCSSR2) and
check that the TDFE flag is set to 1, then
write transmit data to the transmit FIFO
data register 2 (SCFTDR2), read 1 from the
TDFE and TEND flags, then clear these
flags to 0.
The number of transmit data bytes that can
be written is 16 - (transmit trigger set
number).
(2) Serial transmission continuation procedure:
To continue serial transmission, read 1 from
the TDFE flag to confirm that writing is
possible, then write data to SCFTDR2, and
then clear the TDFE flag to 0.
(3) Break output at the end of serial
transmission:
To output a break in serial transmission, set
the port SC data register (SCPDR) and port
SC control register (SCPCR), then clear the
TE bit to 0 in the serial control register 2
(SCSCR2). For information on SCPDR2
and SCPCR2, see section 17.2.8.
In steps 1 and 2, it is possible to ascertain
the number of data bytes that can be
written from the number of transmit data
bytes in SCFTDR indicated by the upper 8
bits of the FIFO data count set register 2
(SCFDR2).
Clear TE bit in SCSCR2 to 0
End of transmission
Figure 19.5 Sample Serial Transmission Flowchart
Rev. 5.00 Dec 12, 2005 page 593 of 1034
REJ09B0254-0500