SH7727 Datasheet, PDF (416/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration
when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value
will enable refreshing to be started immediately.
After self-refreshing has been set, the self-refresh state continues even if the chip standby state is
entered using this LSI's standby function, and is maintained even after recovery from standby
mode other than through a power-on reset. In case of a power-on reset, the bus state controller's
registers are initialized, and therefore the self-refresh state is cleared.
Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in case of a
manual reset. In addition, halt USB and LCDC before entering standby mode.
When the synchronous DRAM is used, self-refreshing is initiated in the following procedure.
1. Clear the refresh control bit to 0.
2. Write H'00 to RTCNT
3. Set the refresh control bit and refresh mode bit to 1.
CKIO, CKIO2
Tp
TRs1
(TRs2)
(TRs2)
TRs3
(Tpc)
(Tpc)
CKE
CSn
RAS3
CAS
RD/WR
Figure 12.20 Synchronous DRAM Self-Refresh Timing
Rev. 5.00 Dec 12, 2005 page 344 of 1034
REJ09B0254-0500