SH7727 Datasheet, PDF (375/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
12.2.5 Individual Memory Control Register (MCR)
The individual memory control register (MCR) is a 16-bit read/write register that specifies RAS
and CAS timing and burst control for synchronous DRAM (areas 2 and 3), specifies address
multiplexing, and controls refresh. This enables direct connection of synchronous DRAM without
external circuits.
The MCR is initialized to H'0000 by power-on resets, but is not initialized by manual resets or
standby mode. The bits TPC1 to TPC0, RCD1 to RCD0, TRWL1 to TRWL0, TRAS1 to TRAS0,
AMX3 to AMX0, and are written to at the initialization after a power-on reset and are not then
modified again. When RFSH and RMODE are written to, write the same values to the other bits.
When using synchronous DRAM, do not access areas 2 and 3 until this register is initialized.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TPC1 TPC0 RCD1 RCD0 TRWL TRWL TRAS TRAS — AMX3 AMX2 AMX1 AMX0 RFSH RMO —
1
0
1
0
DE
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 and 14—RAS Precharge Time (TPC1, TPC0): These bits set the minimum number of
cycles until output of the next bank-active command after precharge, when the synchronous
DRAM interface is selected for external memory. However, the number of cycles inserted
immediately after the precharge all banks (PALL) command is issued when performing auto-
refresh is one fewer than the number of cycles during normal operation.
Description
Bit 15: Bit 14:
TPC1 TPC0 Normal Operation
Immediately After
Precharge Command*
Immediately After
Self-refresh
0
0
1 cycle (Initial value) 0 cycle (Initial value)
2 cycles (Initial value)
1
2 cycles
1 cycle
5 cycles
1
0
3 cycles
2 cycles
8 cycles
1
4 cycles
3 cycles
11 cycles
Note: * Immediately after the precharge all banks (PALL) command is issued when performing
auto-refresh.
Rev. 5.00 Dec 12, 2005 page 303 of 1034
REJ09B0254-0500